1. Field of Invention
This invention relates to a switched capacitor amplifier which is useful in an integrated circuit and capable of operation with reduced power.
2. Description of the Prior Art
FIG. 1 shows a conventional switched capacitor amplifier comprising analog switches 1,2,5,6,7,8,10,11,14,15,16 and 17 (which are represented in the drawing by symbol MOS (metal oxide semiconductor) transistors); capacitors 3,4,12 and 13; transconductance amplifiers 9, 18 (hereinafter often referred to as "amplifiers"); differential input voltage 100 (it is to be understood that reference to voltage and other signals includes the sources of such voltage and other signals); differential output voltage 101; control signals 102,103 for controlling the analog switches; and voltages 104,105 and 106 at the respective points in the figure. The foregoing amplifier is also shown as comprising a half-delay circuit 200a comprising components 1 to 9 and a half-delay circuit 200b comprising components 10 to 18.
Differential input voltage 100 is applied to one end of each of analog switches 1 and 2. The other end of analog switch 1 is connected to one end of each of capacitor 3 and analog switch 5. The other end of analog switch 2 is connected to one end of each of capacitor 4 and analog switch 8. The other end of capacitor 3 is connected to the non-inverting input terminal of amplifier 9 and to one end of analog switch 6. The other end of capacitor 4 is connected to the inverting input terminal of amplifier 9 and to one end of analog switch 7. In addition, the inverting output terminal of amplifier 9 is connected to the other end of each of analog switches 5 and 6 and to one end of analaog switch 10. The non-inverting output terminal of amplifier 9 is connected to the other end of each of analog switches 7 and 8 and to one end of analog switch 11.
Similarly, the other end of analog switch 10 is connected to one end of each of capacitor 12 and analog switch 14. The other end of analog switch 11 is connected to one end of each of capacitor 13 and analog switch 17. The other end of capacitor 12 is connected to the non-inverting input terminal of amplifier 18 and to one end of analog switch 15. The other end of capacitor 13 is connected to the inverting input terminal of amplifier 18 and to one end of analog switch 16. In addition, the inverting output terminal of amplifier 18 is connected to the other end of each of analog switches 14 and 15. The non-inverting output terminal of amplifier 18 is connected to the other end of each of analog switches 16 and 17. The non-inverting and inverting output terminals of amplifier 18 provide a differential output voltage 101.
A control signal 102 is applied to the control input terminal of each of analog switches 1,2,6,7,14 and 17. A control signal is applied to the control input terminal of each of analog switches 5,8,10,11,15 and 16.
The operation of the conventional amplifier of FIG. 1 is described with reference to FIGS. 2(a)-2(g), 3 and 4, wherein FIGS. 2(a)-2(g) are timing diagrams showing how the amplifier operates in terms of timing; and FIGS. 3 and 4 show the connection relationship of the circuit components of FIG. 1 during each timing phase.
As shown in FIGS. 2(a)-2(b), control signals 102 and 103 are clock signals having phases which are opposite to each other. During the phase P001, the control signal 102 is at a high level and control signal 103 is at a low level. Hence, analog switches 1,2,6, 7, 14 and 17 are turned ON, and analog switches 5,8,10,11,15, and 16 are turned OFF.
FIG. 3 shows the connection relationship between amplifiers 9 and 18 and capacitors 3,4,12 and 13 during phase P001 in FIG. 2. That is voltage 104 equals differential input voltage 100 since voltage 100 is applied to one end of each of capacitors 3 and 4.
Amplifier 9 functions as a voltage follower since the inverting output terminal thereof is feedback, i.e. connected, to the non-inverting input terminal thereof, and the non-inverting output terminal thereof is fed back, i.e. connected, to the inverting input terminal thereof. Thus, the input terminals of amplifier 9 serve as artificial ground and an offset voltage Vos9 developes across the input terminals, as shown in FIG. 1.
Accordingly, assuming that the differential voltage 100 is Vin and the voltage 104 is V104, then differential voltage Vc1 retained by capacitors 3 and 4 is: ##EQU1##
During Phase P002, however, control signal 102 is at a low level and control signal 103 is at a high level (see FIGS. 2(a) and 2(b)). Thus, analog switches 1,2,6,7,14 and 17 are turned OFF, and analog switches 5,8,10,11, 15 and 16 are turned ON.
FIG. 4 shows the connection relationship between amplifiers 9 and 18 and capacitors 3,4,12 and 13 during phase P002 of FIG. 2. In other words, a feedback loop is formed via capacitors 3 and 4, in amplifier 9. If the input bias current of amplifier 9 is zero, electric charge injected into capacitors 3 and 4 is not discharged. Hence, capacitors 3 and 4 retain the final value of differential input voltage 100 when control signal 102 changes to a low level state and the control signal 103 changes to a high level state (see FIGS. 2(a), 2(b) and 2(c)).
Assuming the final value of teh differential input voltage 100 is Vk, the differential voltage Vc2 retained by capacitors 3 and 4 is: EQU Vc2=Vk-Vos9 (2)
If we assume voltage 105, which is the output voltage of the amplifier 9, equals V105, then V105 is calculated as follows: ##EQU2## In other words, voltage V105, which is the output voltage of amplifier 9, does not contain the offset voltage Vos9. This means that the offset voltage component of the output voltage provided by half-delay circuit 200a, is corrected.
Similarly, voltage 105 is applied as a differential input signal to half-delay circuit 200b sharing the same structure with half-delay circuit 200a. Since the half-delay circuit 200b operates with the inverse phase of the half-delay circuit 200a, the final value Vk of the differential output voltage 101 is outputted during phase P003 (see FIGS. 2(a)-2(g)). This means that the final voltage level VK retained during phase P001 is outputted with a delay of one clock each for control signals 102 and 103 (see FIGS. 2(a)-2(g)).
As a result, it is possible to correct the offset voltage component of the retained differential input voltage 100 and output the voltage with a delay of one clock, by connecting half-delay circuits 200a and 200b in series and driving the circuits with the phases of the control signlas reversed with respect to each other.
However, in the conventional switched capacitor amplifier of FIG. 1, it is either amplifier 9 or amplifier 18 alone that actually processes the differential input voltage 100. In other words, in the condition shown in FIG. 3, the amplifier 18 retains or amplifies voltage 100, whereas in the condition shown in FIG. 4, amplifier 9 retains or amplifies voltage 100. In either condition, the other amplifier runs through a precharging cycle to correct any offset voltage.
Accordingly, only one half of the entire circuit and consumed power is used effectively to correct the offset voltage. Thus, the remaining half of the circuit and power are wasted. This problem becomes more serious when the amplifier is operated at higher speeds.